Keysight N4903B 12.5 Gb/s BERT System

• >0.5 UI calibrated, compliant and integrated jitter injection: RJ, RJ-LF, RJ-HF, PJ1, PJ2, SJ, BUJ, ISI, sinusoidal interference, triangular and arbitrary SSC and residual SSC
• Excellent signal performance and sensitivity
• Built-in clock data recovery with tunable and compliant loop bandwidth
• Half-rate clocking with variable duty cycle for forwarded clocked devices
• Measures BER, BERT Scan, TJ with RJ/DJ separation, eye diagram, eye mask, BER contour, automated jitter tolerance, pattern capture, frame error rate (FER), or symbol error rate (SER) coded and retimed data streams
• Two adjustable data outputs with independent PRBS and pattern with 120 block pattern sequencer

The J-BERT N4903B high-performance serial BERT provides the most complete jitter tolerance test for embedded and forward clocked devices.

It is the ideal choice for R&D and validation teams characterizing and stressing chips and transceiver modules that have serial I/O ports up to 12.5Gb/s. It can characterize a receiver’s jitter tolerance and is designed to prove compliance to today’s most popular serial bus standards, such as:

• PCI Express® See Measurement Solution 
• SATA/SAS
• DisplayPort
• USB SuperSpeed
• Fibre Channel
• QPI
• Memory buses, such as fully buffered DIMM2
• Backplanes, such as CEI
• 10 GbE/ XAUI
• XFP/XFI, SFP+

Jitter setup screen of J-BERT N4903B	Automated jitter tolerance characterization
Quick eye diagram and mask test	BERT scan with RJ/DJ separation

J-BERT N4903B key benefits:

Accurate characterization is achieved with clean signals from the pattern generator, which features exceptionally low jitter and extremely fast transition times. Built-in and calibrated jitter source allow accurate jitter tolerance testing of receivers.

Test set-up is simplified significantly, because the J-BERT N4903B is designed to match serial bus standards optimally with its differential I/Os, variable voltage levels on most outputs, built-in jitter and ISI, pattern sequencer, reference clock outputs, tunable CDR, pattern capture and bit recovery mode to analyze clock-less and non-deterministic patterns.SER/FER analysis allows jitter tolerance testing of devices using retimed loopback. A second data output with independent pattern memory and PRBS can be used as aggressor channel for crosstalk tests, or when adding channels externally for OOB timing tests or emulation of 3-level signals or signal de-emphasis.

Faster test execution is possible with J-BERT’s automated jitter tolerance tests fast total jitter measurements.

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